m2006-02 datasheet rev 1.0 revised 13jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m2006-02 vcso b ased fec c lock pll integrated circuit systems, inc. product data sheet g eneral d escription the m2006-02 is a vcso (voltage controlled saw oscillator) based clock generator pll designed for clock frequency translation and jitter attenuation. the device supports both forward and inverse fec (forward error correction) clock multiplication ratios. multiplication ratios are pin-selected from pre-programming look-up tables. f eatures pin-selectable pll divider ratios support forward and inverse fec ratio translation, including: ? 255/238 (otu1) mapping and 238/255 de-mapping 255/237 (otu2) mapping and 237/255 de-mapping 255/236 (otu3) mapping and 236/255 de-mapping supports input reference and vcso frequencies up to 700mhz, supports loop timing modes (specify vcso frequency at time of order) low phase jitter < 0.5 ps rms typical (12khz to 20mhz or 50khz to 80mhz) supports active switching between inverse-fec and non-fec clock ratios (same vcso center frequency) ideal for complex ratio fec ratio translation * and for use with an unstable reference ** (i.e., similar to the m2006-12 - and pin-compatible - but without the hitless switching and phase build-out functions) commercial and industrial temperature grades single 3.3v power supply small 9 x 9 mm smt (surface mount) package p in a ssignment (9 x 9 mm smt) figure 1: pin assignment s implified b lock d iagram figure 2: simplified block diagram note *: complex ratio fec ratio translation typically results in low phase detector frequencies. note **: an unstable reference which results in phase detector jitter beyond 2 ns under normal operating conditions example i/o clock frequency combinations using m2006-02-622.0800 and inverse fec ratios fec pll ratio mfec / rfec base input rate 1 (mhz) note 1: input reference clock can be the base frequency shown divided by ?mfin? (as shown in table 3 on pg. 3). output clock (either output) mhz 1/1 622.0800 622.08 or 155.52 238/255 666.5143 237/255 669.3266 236/255 672.1627 table 1: example i/o clock frequency combinations m2006-02 (top view) 18 17 16 15 14 13 12 11 10 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 fin_sel1 gnd nc dif_ref0 ndif_ref0 ref_sel dif_ref1 ndif_ref1 vcc p0_sel p1_sel nfout0 fout0 gnd nfout1 fout1 vcc gnd fin_sel0 fec_sel0 fec_sel1 fec_sel2 fec_sel3 vcc dnc dnc dnc nop_in op_out vc nvc nop_out op_in gnd gnd gnd 19 20 21 22 23 24 25 26 27 rfec div mfec div mfec / rfec divider lut mfin divider lut fin_sel1:0 ref_sel dif_ref0 ndif_ref0 dif_ref1 ndif_ref1 p0_sel p1_sel vcso 0 1 m2006-02 fout0 nfout0 fout1 nfout1 fec_sel3:0 4 2 p0 div (1 or 4) mfin div (1, 4, 8, or 32) p1 div (1 or 4) loop filter m2006-02 vcso based fec clock pll
m2006-02 datasheet rev 1.0 2 of 8 revised 13jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m2006-02 vcso b ased fec c lock pll product data sheet d etailed b lock d iagram figure 3: detailed block diagram p in d escriptions number name i/o configuration description 1, 2, 3, 10, 14, 26 gnd ground power supply ground connections. 4 9 op_in nop_in input external loop filter connections. see figure 4. 5 8 nop_out op_out output 6 7 nvc vc input 11, 19, 33 vcc power power supply connection, connect to + 3.3 v. 12, 13 fout1, nfout1 output no internal terminator clock output pairs. differential lvpecl. 15, 16 fout0, nfout0 17 18 p1_sel p0_sel input internal pull-down resistor 1 p divider controls. lvcmos/lvttl. (for p0_sel, p1_sel , see table 5 on pg. 3. 20 21 ndif_ref1 input internal pull-up resistor 1 reference clock input pair 1. differential lvpecl or lvds. dif_ref1 internal pull-down resistor 1 22 ref_sel input internal pull-down resistor 1 referenc e clock input selection. lvcmos/lvttl: logic 1 selects dif_ref1, ndif_ref1. logic 0 selects dif_ref0, ndif_ref0 . 23 24 ndif_ref0 input internal pull-up resistor 1 reference clock input pair 0. differential lvpecl or lvds. dif_ref0 internal pull-down resistor 1 25 nc no internal connection. 27 28 fin_sel1 fin_sel0 input internal pull-down resistor 1 i nput clock frequency selection. lvcmos/lvttl. (for fin_sel1:0 , see ta b l e 3 on pg. 3. 29 30 31 32 fec_sel0 fec_sel1 fec_sel2 fec_sel3 input internal pull-up resistor 1 fec pll divider ratio selection. lvcmos/ lvttl. (for fec_sel3:0 , see table 4 on pg. 3.) 34, 35, 36 dnc do not connect. internal nodes. connection to these pins can cause erratic device operation. table 2: pin descriptions phase locked loop (pll) m2006-02 saw delay line phase shifter vcso c post c post vc nvc r post nop_out op_out r post r loop r loop c loop c loop r in r in op_in nop_in phase detector loop filter amplifier external loop filter components fout0 nfout0 fec_sel3:0 p0_sel fin_sel1:0 rfec divider mux 0 ref_sel dif_ref1 ndif_ref1 dif_ref0 ndif_ref0 1 fout1 nfout1 p1_sel 2 mfec / rfec divider lut 4 mfin divider lut mfin divider mfec divider p1 divider p = 1 ( p1_sel = 0 ) or 4 ( p1_sel = 1 ) p0 divider p = 1 ( p0_sel = 0 ) or 4 ( p0_sel = 1 )
m2006-02 datasheet rev 1.0 3 of 8 revised 13jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m2006-02 vcso b ased fec c lock pll product data sheet integrated circuit systems, inc. pll d ivider l ook -u p t ables mfin (frequency input) divider look-up table (lut) the fin_sel1:0 pins select the feedback divider value (?mfin?). fec pll ratio dividers look-up table (lut) the fec_sel3:0 pins select the fec feedback and reference divider values mfec and rfec. post-pll dividers the m2006-02 also features two post-pll dividers, one for each output pair. the ?p1? divider is for fout1 and nfout1 ; the ?p0? divider is for fout0 and nfout0 . each divides the vcso frequency to produce one of two output frequencies (1/4 or 1/1 of the vcso frequency). the p1_sel and p0_sel pins each select the value for their corresponding divider. f unctional d escription the m2006-02 is a pll (phase locked loop) based clock generator that generates output clocks synchro- nized to one of two selectable input reference clocks. an internal high "q" saw filter provides low jitter signal performance and controls the output frequency of the vcso (voltage contro lled saw oscillator). configurable fec feedback and reference dividers (the ?mfec divider? and ?rfec divider?) provide the multiplication ratios necessary to accomodate clock translation for both forward and inverse forward error correction. in addition, a configurable feedback divider (labeled ?mfin divider?) provides the broader division options needed to accomodate various reference clock frequencies. for example, the m2006-02-622.0800 (see ?ordering information? on pg. 8 ) has a 622.08 mhz vcso frequency: ? the inverse fec pll ratios (at top of ta bl e 4 ) enable the m2006-02-622.0800 to accept ?base? i nput reference frequencies of: 663.7255 , 666.5143 , 669.3266 , 672.1627 , and 622.08 mhz. ? the mfin feedback divider enables the actual input reference clock to be the ?base? input frequency divided by 1 , 4 , 8 , or 32 . therefore, for the base input frequency of 622.08 mhz, the actual input reference clock frequencies can be: 622.08 , 155.52 , 77.76 , and 19.44 mhz. (see table 3 on pg. 3.) fin_sel1:0 mfin value m2006-02-622.0800 sample ref. freq. (mhz) 1 note 1: example with m2006-02-622.0800 and ?non-fec ratio? selection made from table 4 ( fec_sel2 =1). 11 1 622.08 2 note 2: do not use with fec_sel3:0 =1100 or 1101. 10 4 155.52 0 1 8 77.76 0 0 32 19.44 table 3: mfin (frequency input) divider look-up table (lut) fec_sel3:0 mfec rfec 1 note 1: the phase detector frequenc y (fpd, which is calculated as fref/rfec) should be above 1.5 mhz to prevent spurs on the output clock. to ensure the pll remains locked when using a recovered clock (such as in loop timing mode), the phase detector frequency should ideally be about 20mhz, or at least less than 50 mhz. description 0 0 0 0 236 255 inverse fec ratio 0 0 0 1 79 85 inverse fec ratio, equivalent to 237/255 0 0 1 0 14 15 inverse fec ratio, equivalent to 238/255 0 0 1 1 239 255 inverse fec ratio 0 1 0 0 236 236 non-fec ratio, complements 0000 or 1000 2 note 2: these table selections use the same or similar mfec divider values as the complementary selections noted. this allows the use of the same loop filter component values and resulting pll loop bandwidth and damping factor values for complementary selections. complementary selections can be actively switched in a given application. 0 1 0 1 79 79 non-fec ratio, complements 0001 or 1001 2 0 1 1 0 14 14 non-fec ratio, complements 0010 or 1010 2 0 1 1 1 239 239 non-fec ratio, complements 0011 or 1011 2 1 0 0 0 255 236 fec ratio (otu3) 1 0 0 1 85 79 fec ratio, equivalent to 255/237 (otu2) 1 0 1 0 15 14 fec ratio, equivalent to 255/238 (otu1) 1 0 1 1 255 239 fec ratio 1 1 0 0 1 1 non-fec ratio 3 do not use these two settings with fin_sel1:0= 11 note 3: in non-fec applications, these settings can be used optimize phase detector frequency or to actively change pll loop bandwidth. 1 1 0 1 2 2 1 1 1 0 4 4 non-fec ratio 3 1 1 1 1 8 8 table 4: fec pll ratio dividers look-up table (lut) p1_sel, p0_sel p value m2006-02-622.0800 output frequency (mhz) 1 4 155.52 0 1 622.08 table 5: p divider selector, values, and frequencies
m2006-02 datasheet rev 1.0 4 of 8 revised 13jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m2006-02 vcso b ased fec c lock pll product data sheet the pll the pll uses a phase detector and configurable dividers to synchronize the output of the vcso with selected reference clock. the ?mfin divider? and ?mfec divider? divide the vcso frequency, feeding the result into the phase detector. the selected input reference clock is divided by the ?rfec divider?. the result is fed into the other input of the phase detector. the phase detector compares its two inputs. it then outputs pulses to the loop filter as needed to increase or decrease the vcso frequency and thereby match and lock the divider output?s frequency and phase to those of the input reference clock. due to the narrow tuning range of the vcso (+ 200ppm), appropriate selection of all of the following are required for the pll be able to lock: vcso center frequency, input frequency, and divider selections. maintaining pll lock: the narrow tuning range of the vcso requires that the input reference frequency must remain suitable for the current look-up table selection. for example, when switching between ?inverse fec ratio? and ?non-fec ratio? look-up table selections (see table 4 on pg. 3), the input reference frequency must change accordingly in order for the pll to lock. an out-of-lock condition due to an inappropriate configuration will typically result in the vcso operating at its lower or upper frequency rail, which is approximately 200ppm above or below the nominal vcso center frequency. relationship among frequencies and dividers the vcso center frequency must be specified at time of order. the relationship between the vcso (fvcso) frequency, the mfin divider, the mfec divider, the rfec divider, and the input reference frequency (fin) is: as an example, for the m2006-02-622.0800 , the non-fec and inverse-fec pll ratios in table 4 enable use with these corresponding input reference frequencies: outputs the m2006-02 provides a total of two differential lvpecl output pairs: fout1 and fout0. because each output pair has its own p divider, the fout1 pair and the fout0 can output the two different frequencies at the same time. for example, fout1 can output 155.52 mhz while fout0 outputs 622.08 mhz. any unused output should be left unconnected (floating) in the system application. this will minimize output switching current and therefore minimize noise modulation of the vcso. m2006-02-622.0800 m2006-02-622.0800 vcso clock frequency (mhz) fec ratio = base input ref. frequency (mhz) 1 note 1: input reference clock (?fin?) can be the base frequency shown divided by ?mfin? (as shown in table 3 on pg. 3). 622.08 1 / 1 622.0800 238 / 255 666.5143 237 / 255 669.3266 236 / 255 672.1627 table 6: example fec pll rations and input reference frequencies fvcso fin mfin mfec rfec ------------- - =
m2006-02 datasheet rev 1.0 5 of 8 revised 13jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m2006-02 vcso b ased fec c lock pll product data sheet integrated circuit systems, inc. external loop filter to provide stable pll operation, and thereby a low jitter output clock, the m2006-02 requires the use of an external loop filter. this is provided via the provided filter pins (see figure 4). due to the differential signal path design, the implementation requires two identical complementary rc filters as shown here. figure 4: external loop filter pll bandwidth is affected by the ?mfec? value and the ?mfin? value, as well as the vcso frequency. the various ?non-fec ratio? settings can be used to actively change pll loop bandwidth in a given application. see ?fec pll ratio dividers look-up table (lut)? on pg. 3. consult factory for external loop filter component values. pll simulator tool available a free pc software utility is available on the ics website (www.icst.com). the m2000 timing modules pll simulator is a downloadable application that simulates pll jitter and wander transfer characteristics. this enables the user to set appropriate external loop component values in a given application. go to the saw pll simulator software web page at www.icst.com/products/calculators/m2000filterswdesc.htm c post c post vc nvc r post nop_out op_out r post r loop r loop c loop c loop op_in nop_in 6 7 5 49 8 a bsolute m aximum r atings 1 symbol parameter rating unit v i inputs - 0.5 to v cc + 0.5 v v o outputs - 0.5 to v cc + 0.5 v v cc power supply voltage 4.6 v t s storage temperature - 45 to + 100 o c table 7: absolute maximum ratings note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress sp ecifications only. functional operati on of product at these conditions or any conditions beyond those listed in recommended conditions of operation, dc characteristics, or ac characteristics is not implied. exposure to absolute maximum rating condi tions for extended periods may affect product reliability . r ecommended c onditions of o peration symbol parameter min typ max unit v cc positive supply voltage 3.135 3.3 3.465 v t a ambient operating temperature commercial 0 + 70 o c industrial -40 + 85 o c table 8: recommended conditions of operation
m2006-02 datasheet rev 1.0 6 of 8 revised 13jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. m2006-02 vcso b ased fec c lock pll product data sheet e lectrical s pecifications dc characteristics unless stated otherwise, v cc = 3.3 v + 5 %,t a = 0 o c to + 70 o c (commercial), t a = -40 o c to + 85 o c (industrial), f vcso = f out = 622-675 mhz, lvpecl outputs terminated with 50 ? to v cc - 2v symbol parameter min typ max unit conditions power supply v cc positive supply voltage 3.135 3.3 3.465 v i cc power supply current 175 225 ma all differential inputs v p - p peak to peak input voltage dif_ref0, ndif_ref0, dif_ref1, ndif_ref1 0.15 v v cmr common mode input 0.5 v cc - .85 v c in input capacitance 4 pf differential inputs with pull-down i ih input high current (pull-down) dif_ref0, dif_ref1 150 a v cc = v in = 3.456v i il input low current (pull-down) - 5 a r pulldown internal pull-down resistance 50 k ? differential inputs with pull-up i ih input high current (pull-up) ndif_ref0, ndif_ref1 5 a v in = 0 to 3.456v i il input low current (pull-up) - 150 a r pullup internal pull-up resistance 50 k ? all lvcmos / lvttl inputs v ih input high voltage ref_sel, fin_sel1, fin_sel0, fec_sel3, fec_sel2, fec_sel1, fec_sel0, p1_sel, p0_sel 2 v cc + 0.3 v v il input low voltage - 0.3 0.8 v c in input capacitance 4 pf lvcmos / lvttl inputs with pull-down i ih input high current (pull-down) ref_sel, fin_sel1, fin_sel0, p1_sel, p0_sel 150 a v cc = v in = 3.456v i il input low current (pull-down) - 5 a r pulldown internal pull-down resistance 50 k ? lvcmos / lvttl inputs with pull-up i ih input high current (pull-up) fec_sel3, fec_sel2, fec_sel1, fec_sel0 5 a v cc = 3.456v v in = 0 v i il input low current (pull-up) -1 50 a r pullup internal pull-up resistance 50 k ? differential outputs v oh output high voltage fout0, nfout0, fout1, nfout1 v cc - 1.4 v cc - 1.0 v v ol output low voltage v cc - 2.0 v cc - 1.7 v v p - p peak to peak output voltage 1 note 1: single-ended measurement. see figure 5, output rise and fall time, on pg. 7. 0.4 0.85 v table 9: dc characteristics
m2006-02 datasheet rev 1.0 7 of 8 revised 13jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 m2006-02 vcso b ased fec c lock pll product data sheet integrated circuit systems, inc. e lectrical s pecifications ( continued ) p arameter m easurement i nformation output rise and fall time figure 5: output rise and fall time output duty cycle figure 6: output duty cycle ac characteristics unless stated otherwise, v cc = 3.3 v + 5 %,t a = 0 o c to + 70 o c (commercial), t a = -40 o c to + 85 o c (industrial), f vcso = f out = 622-675 mhz, lvpecl outputs terminated with 50 ? to v cc - 2v symbol parameter min typ max unit test conditions input frequency range f in input frequency dif_ref0, ndif_ref0, dif_ref1, ndif_ref1 10 700 mhz output frequency f fout output frequency range fout0, nfout 0, fout1, nfout 1 100 700 mhz apr vcso pull-range commercial 120 200 ppm industrial 50 150 ppm pll loop constants 1 note 1: parameters needed for pll simulator softwar e; see pll simulator tool available on pg. 5. k vco vco gain 800 khz/v r in internal loop resistor 50 k ? bw vcso vcso bandwidth 700 khz phase noise and jitter n single side band phase noise @ 622.08 mhz 1 khz offset - 72 dbc/hz fin=19.44 mhz mfin=32, mfec=1, rfec=1 10 khz offset - 94 dbc/hz 100 khz offset - 123 dbc/hz j(t) jitter (rms) @ 622.08 mhz 12khz to 20mhz 0.5 ps rms 50khz to 80mhz 0.5 ps rms t pw output duty cycle 2 fout0, nfout 0, fout1, nfout 1 note 2: see parameter measurement information on pg. 7. p0, p1 = 1 40 50 60 % p0, p1 = 4 45 50 55 % t r output rise time 2 fout0, nfout 0, fout1, nfout 1 200 450 500 ps 20 % to 80 % t f output fall time 2 200 450 500 ps 20 % to 80 % table 10: ac characteristics 20% 80% t r 20% t f 80% clock output v p - p nfout fout t pw t period (output pulse width) t period t pw odc =
m2006-02 datasheet rev 1.0 8 of 8 revised 13jul2004 integrated circuit systems, inc. networking & communications www.icst.com tel (508) 852-5400 integrated circuit systems, inc. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high reliability, or other extraordina ry environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. m2006-02 vcso b ased fec c lock pll product data sheet d evice p ackage - 9 x 9mm c eramic l eadless c hip c arrier mechanical dimensions: figure 7: device package - 9 x 9mm ceramic leadless chip carrier o rdering i nformation part numbering scheme figure 8: part numbering scheme standard vcso output frequencies (mhz) * consult ics for the availablity of other vcso frequencies consult ics for the availabilit y of other pll frequencies. refer to the m2006-02 product web page at www.icst.com/products/summary/m2006-02.htm for application notes, including recommended pcb footprint, solder mask, and furnace profile. see table 11, right. consult ics for other frequencies. part number: m2006- 02 - xxx.xxxx vcso frequency (mhz) ? - ? = 0 to + 70 o c (commercial) i = - 40 to + 85 o c (industrial) temperature device number note *: fout can equal fvcso divided by: 1 or 4 622.0800 669.3120 625.0000 669.3266 627.3296 669.6429 644.5313 670.8386 666.5143 672.1600 669.1281 690.5692 table 11: standard vcso output frequencies (mhz) example part numbers pll frequency (mhz) temperature order part number 622.08 commercial m2006-02 - 622.0800 industrial m2006-02 i 622.0800 625.00 commercial m2006-02 - 625.0000 industrial m2006-02 i 625.0000 669.3266 commercial m2006-02 - 669.3266 industrial m2006-02 i 669.3266 669.6429 commercial m2006-02 - 669.6429 industrial m2006-02 i 669.6429 table 12: example part numbers
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